Imagine a breakthrough that could revolutionize how we develop and stack microchips—this is precisely what CEA-Leti has achieved with its latest milestone in semiconductor fabrication. But here's where it gets controversial: the institute has successfully produced working CMOS (Complementary Metal-Oxide-Semiconductor) chips operating at just 400°C, a temperature significantly lower than traditional methods. This advancement allows the chips to be stacked vertically—layer upon layer—without risking thermal damage to the underlying circuitry, a challenge that has long impeded progress toward creating more compact, efficient, and high-performance 3D chip structures.
CEA-Leti, a prominent French research organization spearheading the EU’s FAMES pilot line, revealed that these low-temperature fabricated devices maintain electrical performance levels comparable to those manufactured at conventional high temperatures exceeding 1,000°C. The findings were detailed in a comprehensive paper presented at the International Electron Devices Meeting held in San Francisco. The key to this achievement lies in innovative techniques like nanosecond laser annealing, which is used to activate doping agents (dopants) and convert silicon in a controlled manner. This approach paves the way for stacking multiple layers—forming complex, multi-tier chips that integrate logic, radio frequency (RF), sensors, and other functionalities—aligning perfectly with the EU’s strategic push for semiconductor independence under the Chips Act.
The core advantage of the 400°C process is that it permits the layering of CMOS components atop fully fabricated circuitry without breaching thermal thresholds that could otherwise compromise or damage earlier layers. This capability facilitates the development of highly integrated systems combining core logic functions with RF modules, smart pixel arrays, or power management units, all in a compact three-dimensional form.
The FAMES project, established in 2023 as part of the EU Chips Act strategy, centers on advanced FD-SOI (Fully Depleted Silicon On Insulator) platforms and applications beyond traditional Moore’s Law scaling, known as more-than-Moore. The consortium is a collaboration among multiple research leaders, including CEA-Leti, imec, Fraunhofer, VTT, CEZAMAT WUT, Tyndall, Silicon Austria Labs, and several universities across Europe. Together, they aim to push the boundaries of semiconductor technology.
An exciting example of this technological leap is the concept of a three-layer micro-LED GaN (Gallium Nitride) pixel array, which uses 3D sequential integration (3DSI) and hybrid bonding techniques for a dense, high-emission display. CEA-Leti’s 400°C CMOS process supports such top-tier stacking without exceeding the thermal limits of underlying active circuitry, opening new possibilities for compact, multi-functional optoelectronic devices.
And this is the part most people miss—the ability to stack layers without damage at such low temperatures not only accelerates advances in 3D integration but also challenges long-held assumptions about manufacturing constraints. But here’s a question to ponder: should we be skeptical of claims that lower processing temperatures can fully replace high-temperature methods without trade-offs? Or could this innovation herald a new era where multi-layered semiconductor devices become more accessible and cost-effective? Join the conversation and share your thoughts!
